Capping of copper structures in hydrophobic ild using aqueous electro-less bath

ABSTRACT

Capping of copper structures in hydrophobic interlayer dielectric layer, using aqueous electro-less bath is described herein.

RELATED APPLICATION

The present application is a divisional of U.S. patent application Ser. No. 10/814,592, filed Mar. 31, 2004, and entitled “Capping of Copper Structures in Hydrophobic ILD Using Aqueous Electro-Less Bath,” which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD & BACKGROUND

The present invention is related to the field of integrated circuits. More specifically, the present invention is related to the formation of cobalt caps on copper interconnects.

Recently, there is increasing interest in the semiconductor industry to reduce the defects on copper interconnects and properly add a cobalt capping layer to each of the copper interconnects. One area of difficulty preventing the accomplishment of low or no defects and even deposition of a cobalt capping layer on each of the copper interconnects is the cobalt wetting problem. The cobalt wetting problem involves the difficulty of electro-less cobalt solutions evenly wetting the top surface of each of the copper interconnects. Also the wetting problem increases the amount of cobalt particles that get adhered to undesired areas on the wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which:

FIG. 1 illustrates a cross sectional view of a portion of a component showing a cobalt capping layer and little or no cobalt particles on the interlayer dielectric layer, in accordance with one embodiment;

FIGS. 2 a-2 b illustrate a method for making the wafer of FIG. 1, in accordance with one embodiment;

FIG. 3 illustrates a block diagram view of a system for making the wafer of FIG. 1, in accordance with one embodiment; and

FIG. 4 illustrates a block diagram view of a system having the wafer of FIG. 1 in accordance with one embodiment.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Embodiments of the present invention include, but are not limited to, a component having the formation of cobalt caps on copper interconnects, method for making such component, and system having such component.

Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

The phrase “in one embodiment” is used repeatedly. The phrase generally does not refer to the same embodiment, however, it may. The terms “comprising”, “having” and “including” are synonymous, unless the context dictates otherwise.

Referring now to FIG. 1, wherein a cross sectional view of a portion of a component showing a cobalt capping layer and little or no cobalt particles on the interlayer dielectric layer, in accordance with one embodiment. As illustrated, for the embodiment, wafer 100 includes an interlayer dielectric layer 102 and a number of copper structures 104 disposed on the interlayer dielectric layer 102. Shown in FIG. 1 is a cobalt barrier layer 106 disposed on a top surface 108 of one of the copper structures 104. Copper structure 104 with cobalt barrier layer 106 may also be referred to as copper structure with capping layer 110 and copper structure without cobalt barrier layer 106 may be referred to as a copper structure without a capping layer 112 as shown.

In various embodiments, the interlayer dielectric layer (ILD) 102 is a partially or fully hydrophobic low K ILD. That is, ILD 102 is of a type that is adverse to an aqueous (water) based solution, resulting in higher surface tension adverse to the aqueous based solution, which in turn may lead to the uneven wetting of the top surface of the partially or fully hydrophobic low K ILD. An example of a hydrophobic low K ILD is a low K Si—O ILD having methyl content. In various embodiments, the low K dielectric constant value is 3.5 or lower.

As will be described in more detail below, the cobalt barrier layer 106 is deposited on the top surface 108 using an aqueous cobalt electro-less bath assisted by sonic energy to reduce the surface tension, contributing to the interlayer dielectric layer 102 having lower or substantially free of adhered cobalt particles 114. Substantially free is with little or no cobalt particles 114 on the interlayer dielectric layer 102. The sonic energy aids in the thorough and homogeneous deposition of cobalt onto the top surface 108. The sonic energy also reduces the surface tension for the electro-less solution, increasing the wettability of the top surface 108.

In various embodiments, the interlayer dielectric layer 102 may have lower or substantially free of adhered particles 114 due to further simultaneous rinsing and applying of sonic energy to the interlayer dielectric layer 102 together, after deposition of the cobalt barrier layer 106.

The sonic energy, whether it is applied during deposition or rinsing may be a selected one of mega and ultra sonic energy. The sonic energy may be in a frequency range of 10 to 1200 kiloHertz and power in the range of 1 to 5 Watts/cm². The sonic energy may be applied during a portion or the entire duration of deposition/rinsing.

In various embodiments, the sonic energy applied during deposition and rinsing may be of the same or different type, same or different frequency, as well as same or different power.

FIGS. 2 a-2 b illustrate a method of making wafer 100 in accordance with one embodiment. The embodiment wafer 100 has a hydrophobic interlayer dielectric layer 122 (hereinafter, simply interlayer dielectric layer) and a plurality of copper structures 124 partially encased in an interlayer dielectric layer 122. Top surfaces 128 of the copper structures 124 are exposed and substantially co-planar with a top surface of the interlayer dielectric layer 130. A cobalt barrier layer 126 is selectively deposited on the top surface of the plurality of copper structures 124, using an aqueous electro-less cobalt bath, assisted by application of the sonic energy. By applying sonic energy during deposition, substantially less, or possibly no deposition of cobalt 134 on the top surface of the interlayer dielectric layer 130 may be effectuated.

In various embodiments, the interlayer dielectric layer 122 may also have sonic energy simultaneously applied while the top surface is being rinsed after deposition. The combined simultaneous rinse and application of sonic energy, after deposition, may further contribute to the decrease of the amount of cobalt particles adhered to the interlayer dielectric layer 122.

As described earlier, the sonic energy may be applied for a portion or the entire duration of the deposition/rinsing. The sonic energy may be a selected one of mega and ultra sonic energy, of a selected frequency between 10 and 1200 Hertz, and of a power level between 1 and 5 Watts/cm².

FIG. 3 illustrates a block diagram view of a system suitable for use to practice the sonic energy augmented process for forming cobalt caps on copper structures disposed on a hydrophobic interlayer dielectric layer, in accordance with one embodiment. As illustrated, system 300 includes chamber 302 adapted for cobalt deposition to form the cobalt capping on copper structures disposed on a hydrophobic interlayer dielectric layer. Chamber 302 includes a substrate holder 304 for holding the substrate with the hydrophobic interlayer dielectric layer having copper structures to be cobalt capped.

Additionally, for the embodiment, system 300 includes sonic energy generator 308 coupled to chamber 302 to allow sonic energy to be generated and provided to chamber 302 during the cobalt deposition process, as earlier described.

Further, for the embodiment, system 300 includes one or more tanks coupled to chamber 302 to store and provide chamber 302 with an aqueous electro-less solution for the rinsing operation earlier described. For the embodiment, sonic generator 308 is also adapted to allow sonic energy to be generated and provided to chamber 302 during the rinsing process, as earlier described.

Except for the novel employment of sonic energy generator 308 to generate and provide sonic energy to augment the cobalt deposition and/or the rinsing process, chamber 302, tanks 306 and sonic energy generator 308 may be implemented in any one of a variety of manners.

FIG. 4 illustrates a block diagram view of a system having a semiconductor package with a die having copper structures cobalt capped as earlier described, in accordance with one embodiment. As illustrated, for the embodiment, system 400 includes a communication interface 402 coupled to a bus 404. The bus 404 is coupled to the semiconductor package 406 and the semiconductor package 406 comprises a die 408. The die 408 has a hydrophobic interlayer dielectric layer and a plurality of copper structures disposed thereon. Further, a cobalt barrier layer is deposited on a top surface of each of the plurality of copper structures, as earlier described. The interlayer dielectric layer has a decreased amount of cobalt deposition that may be effectuated by augmenting the cobalt deposition process, and/or the post-deposition rinsing process, with sonic energy, as earlier described with reference to FIG. 2.

In various embodiments, semiconductor package 406 may be a microprocessor, a memory device, a graphics processor, a crypto processor, digital signal processor, or other semiconductor devices of the like.

In various embodiments, system 400 may be a wireless mobile phone, a personal digital assistant, a tablet computer, a laptop computer, a desktop computer, a server, a digital camera, a digital versatile disk player, an audio/video media play, or a set-top box. Communication interface 402 may be a networking interface.

Thus, it can be seen from the above descriptions, a novel component having the formation of cobalt caps on copper interconnects, method for making such a component, and a system having such a component have been described. While the present invention has been described in terms of the foregoing embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described. The present invention can be practiced with modification and alteration within the spirit and scope of the appended claims.

Thus, the description is to be regarded as illustrative instead of restrictive on the present invention. 

1. An apparatus comprising: a chamber adapted for cobalt deposition, including a holder to hold a substrate with a hydrophobic interlayer dielectric layer; and a sonic energy generator coupled to the chamber and adapted to allow sonic energy be applied during deposition of cobalt to cap a number of copper structures disposed on the hydrophobic interlayer dielectric layer.
 2. The apparatus of claim 1, wherein the apparatus further comprises at least one tank coupled to the chamber and adapted to store and to provide the interlayer dielectric layer with an aqueous electro-less bath; and the sonic energy generator is also adapted to allow sonic energy be applied during the provision of the aqueous electro-less bath.
 3. The apparatus of claim 1, wherein the sonic energy generator is adapted to apply a selected one of mega and ultra sonic energy.
 4. The apparatus of claim 1, wherein the sonic energy generator is adapted to apply the sonic energy at a frequency range of 10 to 1200 kilohertz.
 5. The apparatus of claim 1, wherein the sonic energy generator is adapted to apply the sonic energy at a power level in a range of 1 to 5 watts/cm².
 6. An apparatus comprising: a chamber including a holder to hold a substrate with a hydrophobic interlayer dielectric layer; at least one tank coupled to the chamber and adapted to store and to provide the interlayer dielectric layer with an aqueous electro-less bath; and a sonic energy generator coupled to the chamber and adapted to allow sonic energy be applied during the provision of the aqueous electro-less bath.
 7. The apparatus of claim 6, wherein the sonic energy generator is adapted to apply a selected one of mega and ultra sonic energy.
 8. The apparatus of claim 6, wherein the sonic energy generator is adapted to apply the sonic energy at a frequency range of 10 to 1200 kilohertz.
 9. The apparatus of claim 6, wherein the sonic energy generator is adapted to apply the sonic energy at a power level in a range of 1 to 5 watts/cm².
 10. An apparatus comprising: a hydrophobic interlayer dielectric layer substantially free of adhered cobalt particles; a copper structure disposed on the interlayer dielectric layer; and a cobalt capping layer disposed on a top surface of the copper structure.
 11. The apparatus of claim 10, wherein the hydrophobic interlayer dielectric layer has a low K value where K is a dielectric constant lower than 3.5.
 12. A system comprising: a semiconductor package comprising a die, the die having a hydrophobic interlayer dielectric layer that is substantially free of adhered cobalt, and a plurality of cobalt capped copper structures disposed on the interlayer dielectric layer; a bus coupled to the semiconductor package; and a network interface module coupled to the bus.
 13. The system of claim 12, wherein the semiconductor package comprises a semiconductor device selected from a semiconductor device group consisting of a microprocessor, a memory device, a graphics processor, a digital signal processor, and a crypto processor.
 14. The system of claim 13, wherein the system is a selected one of a a digital versatile disk player, an audio/video media player, and a set-top box. 